The format of the input data (read data) of phase synchronization circuits of magnetic disk devices such as a floppy disk consists of a synchronization field (SYSC) having synchronization beats of equally spaced pulsed strings at a heading portion between adjacent juncture fields (GAP) and an information field (an index field (ID) and a data field (DATA)) having synchronization beats and data beats which follow the synchronization field. Therefore, whilst the PLL circuit is locked by operating the synchronization field preceding the information field so as to bring the PLL circuit into a synchronization-locked state, the PLL circuit operates so as to continue to keep the synchronization at the same repetition frequency in the information field. A PLL circuit in a floppy disk device, such as that disclosed in Japanese Patent Publication Number S 58-50827 is well known. In this phase synchronization circuit, when the read data (RD), reproduced by a floppy disk device, is in the synchronization field within that sector, in order to bring the PLL circuit itself into a synchronization-locked state, a frequency and phase comparator and a low pass filter (LPF) with a high gain are chosen such that synchronization beats are followed at high speed, and when the read data RD is in the data field, a phase comparator which compares phases only and a low pass filter with a low gain which does not follow the peak shift of the data beats, are chosen because the PLL circuit has already been in synchronization. In the method wherein the combination of the frequency and phase comparator and the low pass filter with a high gain and the combination of the phase comparator and the low pass filter with a low gain are controlled to be switched between the synchronization fields and the data fields, there is provision for avoiding erroneous locking and increasing the speed of lock-in operation or stabilizing the reading operation.
Problems with the PLL circuits according to the above configuration are described below.
Since a frequency and phase comparator are required, a low pass filter must be provided after each of them. In general, the low pass filter is a lag lead filter which is equivalent to a charge pump in front of it with regard to circuit correlation and is a series circuit comprising a resistor element and a capacitor element but if a plurality of low pass filters are used, they will consume a large part of the space for both packaging because the number of discrete parts will increase. When the phase synchronization circuit is implemented on a single semiconductor integrated circuit chip, the size of the chip will increase because a plurality of low pass filters must be formed.
When a two-seven RLL recording method wherein the frequency of synchronization beats and the oscillation frequency of a voltage controlled oscillator which is frequency-controlled by the output potential of a low pass filter are different, is employed, it is not possible to simply use a frequency and phase comparator as it is.